Define DFT architecture, integrate DFT RTL, perform scan insertion, ATPG, memory BIST, and support silicon bringup.
Drive end-to-end security architecture for next-generation SoCs, including Root of Trust, Key Management, and Crypto Accelerators.
Responsible for chip level STA convergence from early stages to signoff, including timing constraints, multimode-multi corner analysis, and ECO generation.
Perform C & SV/UVM based verification, write testcases and testbenches, and handle IP & SoC level verification for ARM/RISC-V based SoCs.
Develop synthesizable RTL using Verilog/SystemVerilog, define micro-architecture, and integrate digital IPs into top-level SoC.
Drive Specifications, Architecture and Design of Analog IPs, including Data Converters, Power Management, Battery Charging Circuits, PLLs, and other Analog IPs.